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| 1 an30183a ver. aeb 600ma synchronous dc-dc step down regulator (1ch) 300ma ldo regulator (4ch) multi power supply (high efficiency power lsi) z high-speed response dc-dc step down regulator circuit that employs hysteretic system z dc-dc step down regulator : 1-ch input voltage range vbat :2.5v to 5.5v dvdd : 1.7v to 3.0v output voltage range 0.8 v to 2.4 v up to 600 ma output current z ldo regulator : 4-ch input voltage range vbat :2.5v to 5.5v dvdd : 1.7v to 3.0v output voltage range 1.0 v to 3.3 v up to 300 ma output current z i 2 c control (2-slave address selectable) z 20 pin wafer level chip size package (wlcsp) (size : 1.56 mm 2.06 mm, 0.4 mm pitch) mobile phone, portable appliance, etc simplified application applications features description an30183a is a multi power supply lsi which has high- speed response dc-dc step down regulators (1-ch) and ldo regulators (4-ch). by this dc-dc system, when load current charges suddenly, it responds at high speed and minimizes the changes of output voltage. since it is possible to use capacitors with small capacitance and it is unnecessary to add external parts for system phase compensation, this ic realizes downsizing of set and reducing in the number of external parts. the output dc of each power supply is variable by i 2 c control. notes) this application circuit is an example. the operation of mass production set is not guaranteed. you should perform enough evaluation and verification on the design of mass production set. you are fully responsible for the incorporation of the above application circuit and information in the design of your equipment. condition ) ddvbat1 = ddvbat2 = vb = vin2 = 3.7v lo = 1.0 h, cout = 4.7 f dcdcout1 ddvbat1 vin2 vb an30183a agnd vreg vldo4 vldo3 vldo2 vldo1 ref lx1 fb1 ddgnd1 dvdd reset ldo1on sda scl asel 1 f 1 f 1 f 1 f 1 f 1 f 1 h 4.7 f 4.7 f4.7 f 4.7 f 0.1 f regcnt an30183a dcdc1 efficiency 0 10 20 30 40 50 60 70 80 90 100 1 10 100 1000 load current [ma] efficiency [%] vout=0.8v vout=1.2v vout=1.8v vout=2.4v efficiency curve publication date: october 2012
2 an30183a ver. aeb absolute maximum ratings *1 *3 v ? 0.3 to v vbat + 0.3 lx1,vreg,ref,sda ldo1,ldo2,ldo3,ldo4 output voltage range *1 *3 v ? 0.3 to dvdd + 0.3 scl,sda,asel *1 *3 v ? 0.3 to v vbat + 0.3 reset,ldo1on,fb1, regcnt input voltage range *1 v 3.6 dvdd ? kv 2 hbm (human body model) esd *2 c ? 30 to + 150 t j operating junction temperature *2 c ? 55 to + 150 t stg storage temperature *1 a ? i in output current notes unit rating symbol parameter *2 c ? 30 to + 85 t opr operating free-air temperature *1 v 6.0 vb,vin2,ddvbat1 supply voltage notes) do not apply external currents and voltages to any pin not specifically mentioned. this product may sustain permanent damage if subjected to conditions higher than the above stated absolute maximum rating. this rating is the maximum rating and device operating at this range is not guaranteeable as it is higher than our stated recommended operating range. when subjected under the absolute maximum rating for a long time, the reliability of the product may be affected. *1:the values under the condition not exceeding the above absolute maximum ratings and the power dissipation. *2:except for the power dissipation, operating ambient temperature, and storage temperature, all ratings are for ta = 25 c. *3:v vbat is voltage for ddvbat1 = vb = vin2, (v vba + 0.3) v must not be exceeded 6 v. v dvdd is voltage for dvdd, (v dvdd + 0.3) v must not be exceeded 3.6 v. *1 notes 0.181 w 0.348 w 359.0 c / w 20 pin wafer level chip size package (wlcsp type) pd ( ta = 85 c) pd ( ta = 25 c) ja package power dissipation rating note). for the actual usage, please refer to the pd-ta characteristics diagram in the package specification, follow the power s upply voltage, load and ambient temperature conditions to ensure that there is enough margin and the thermal design does not exceed the allowable value. *1:glass epoxy substrate ( 4 layers ) [ glass-epoxy: 50 x 50 x 0.8 t ( mm ) ] die pad exposed , soldered. caution although this has limited built-in esd protection circuit, but permanent damage may occur on it. therefore, proper esd precautions are recommended to avoid electrostatic damage to the mos gates 3 an30183a ver. aeb recommended operating conditions *2 v dvdd + 0.3 ? ?0.3 sda *2 v v vbat + 0.3 ? ?0.3 ref *2 v v vbat + 0.3 ? ?0.3 vldo1 *2 v v vbat + 0.3 ? ?0.3 vldo2 *2 v v vbat + 0.3 ? ?0.3 vldo3 *2 v v vbat + 0.3 ? ?0.3 vldo4 *2 v v vbat + 0.3 ? ?0.3 vreg output voltage rang *2 v v vbat + 0.3 ? ?0.3 fb1 *2 v v vbat + 0.3 ? ?0.3 regcnt *2 v v vbat + 0.3 ? ?0.3 ldo1on *2 v dvdd + 0.3 ? ?0.3 scl *1 v 5.5 3.7 2.5 ddvbat1 *1 v 5.5 3.7 2.5 vin2 *2 v v vbat + 0.3 ? ?0.3 lx1 v v vbat + 0.3 ? ?0.3 reset *1 v 3.0 1.85 1.7 dvdd *2 v dvdd + 0.3 ? ?0.3 sda ? 3.7 typ. *2 input voltage range *2 v dvdd + 0.3 ?0.3 asel 2.5 min. *1 v 5.5 vb supply voltage range notes unit max. pin name parameter note) do not apply external currents and voltages to any pin not specifically mentioned. voltage values, unless otherwise specified, are with respect to gnd. gnd is voltage for agnd = ddgnd1 v vbat is voltage for ddvbat1 = vb = vin2. *1 : the values under the condition not exceeding the above absolute maximum ratings and the power dissipation. *2 : (v vbat + 0.3) v must not be exceeded 6 v. (dvdd + 0.3) v must not be exceeded 3.6 v. 4 an30183a ver. aeb elecrtrical characteristics v vbat (ddvbat1 = vb = vin2) = 3.7v, dvdd = 1.85v dc-dc : co = 4.7 f, lo = 1 h / ldo : co =1.0 f t a = 25 c 2 c unless otherwise noted. ? a 1.0 0.1 ? dcdc1, ldo1-4 = off reset = ?l? ibat_3 static consumption current consumption current ? a 400 240 ? dcdc1, ldo1-4 = on ibat_2 consumption current 2 on active ? a 20 10 ? only ldo1 (ps mode) on ibat_1 consumption current 1 on active limits typ unit max notes min conditions symbol parameter 5 an30183a ver. aeb elecrtrical characteristics (continued) v vbat (ddvbat1 = vb = vin2) = 3.7v, dvdd = 1.85v dc-dc : co = 4.7 f, lo = 1 h / ldo : co =1.0 f t a = 25 c 2 c unless otherwise noted. ldo1 ? 4 ( power save mode ) - (ldo regulator) ? mv 25 0 ?25 vb = 3.1 v 4.5 v ildo = ? 5 ma vout = 1.85 v setting vldolrps line regulation ? mv 50 20 ?5 ildo = ? 10 a ?5 ma dvldops load regulation ? ma ? ? 10 ? ildops output current ? v 1.897 1.850 1.803 ildo = ? 5 ma vout = 1.85 v setting vldops output voltage ? ma 255 100 35 vb = 3.7 v vldo = 0 v istldo short-circuit current ? mv 10 0 ?10 vb = 3.1 v 4.5 v ildo = ? 150 ma vout = 1.85 v setting vldolr line regulation ? mv 50 20 ?5 ildo = ? 10 a ? 150 ma dvldo load regulation ldo1 ? 4 ( normal mode ) - (ldo regulator) ? ma ? ? 300 ? ildo output current ? v 1.897 1.850 1.803 ildo = ? 150 ma vout = 1.85 v setting vldo output voltage limits typ unit max notes min conditions symbol parameter 6 an30183a ver. aeb ? v ? ? v dvdd 0.7 voltage recognized as high level vih2 high input voltage ? v v dvdd 0.3 ? ? voltage recognized as low level vil2 low input voltage i/o characteristics of control terminal (asel) ? m 6 3 1 ? pdr1 input pull-down resistance ? v ? ? 1.2 voltage recognized as high level vih1 high input voltage ? v 0.45 ? ? voltage recognized as low level vil1 low input voltage i/o characteristics of control te rminal (reset, ldo1on, regcnt) ? mhz 4 3 2 idcdc1 = ? 300 ma (ccm) istdcdc1 oscillation frequency ? mv 13 4 ? ddvbat1 = 3.1 v 4.5 v idcdc1 = ? 300 ma vout = 1.2 v setting vdcdc1lr line regulation ? mv 45 25 ? idcdc1 = ? 10 a ? 500 ma vout = 1.2 v setting dvdcdc1 load regulation dcdc1 (dc-dc step down regulator) ? ma ? ? 600 ? idcdc1 output current ? v 1.230 1.200 1.170 idcdc1 = ? 300 ma vout = 1.2 v setting vdcdc1 output voltage limits typ unit max notes min conditions symbol parameter elecrtrical characteristics (continued) v vbat (ddvbat1= vb = vin2) = 3.7v, dvdd = 1.85v dc-dc : co = 4.7 f, lo = 1 h / ldo : co =1.0 f t a = 25 c 2 c unless otherwise noted. 7 an30183a ver. aeb *2 khz 400 ? 0 ? fosc scl clock frequency *2 a 10 ? ?10 scl, sda = 0.1 v dvddmax to 0.9 v dvddmax il input current each i/o pin *2 v 0.2 v dvdd ? 0 v dvdd < 2 v sda(sink current) = 3 ma vol2 low-level output voltage 2 *2 v 0.4 ? 0 v dvdd > 2 v sda(sink current) = 3 ma vol1 low-level output voltage 1 i 2 c bus (internal i/o stage characteristics) *1 *2 v v dvdd max + 0.5 ? 0.7 v dvdd voltage which recognized that sda and scl are high-level vih1 high-level input voltage *1 *2 v 0.3 v dvdd ? ?0.5 voltage which recognized that sda and scl are low-level vil1 low-level input voltage reference values typ unit max notes min conditions symbol parameter application information reference values for design v vbat (ddvbat1 = vb = vin2) = 3.7v, dvdd = 1.85v t a = 25 c 2 c unless otherwise noted. notes) *1 : the input threshold voltage of i 2 c bus (vth) is linked to v dvdd. in case the pull-up voltage is not v dvdd , the threshold voltage (vth) is fixed to ((v dvdd / 2) (schmitt width) / 2 ) and high-level, low-level of input voltage are not specified. in this case, pay attention to low-level (max.) value (v ilmax ). it is recommended that the pull-up voltage of i 2 c bus is set to the i 2 c bus i/o stage supply voltage (v dvdd ). *2 :checked by design, not production tested. 8 an30183a ver. aeb *2 a 75 50 25 normal mode vb > vout + 0.1 v or vin2 > vout + 0.1 v iregldo consumption current on active ldo1 ? 4 ( power save mode ) - (ldo regulator) *2 ma 40 20 5 vb = 3.7 v vldo = 0 v istldops short-circuit current *2 db ?5 ?10 ? vb = 3.7 v 0.15 v ildo = ? 5 ma fvin = 100 hz to 10 khz vldopsrr ripple rejection *2 a 5 3 1 power save mode vb > vout + 0.1 v or vin2 > vout + 0.1 v iregldops consumption current on active *2 v 1.897 1.850 1.803 ildo = ? 5 ma vout = 1.85 v setting vldops output voltage *2 mv 150 30 ? ildo = ? 10 a ? ? 100 ma ltrldo load change characteristic *2 k 200 100 50 ? rdisldo discharge resistance *2 db ?40 ?60 ? vb = 3.7 v 0.15 v ildo = ? 150 ma fvin = 100 hz to 10 khz vldorr ripple rejection ldo1 ? 4 ( normal mode ) - (ldo regulator) *2 v ? ? 0.3 ildo = ? 300 ma vsatldo i/o voltage difference *2 v 1.897 1.850 1.803 ildo = ? 150 ma vout = 1.85 v setting vldo output voltage reference values typ unit max notes min conditions symbol parameter application information (continued) reference values for design v vbat (ddvbat1 = vb = vin2) = 3.1v to 4.5v, v dvdd = 1.85v , dc-dc : co = 4.7 f, lo = 1 h / ldo : co =1.0 f t a = 25 c 2 c unless otherwise noted. notes) *2 :checked by design, not production tested. 9 an30183a ver. aeb *2 k 2.0 1.0 0.5 ? rdisdcdc1 discharge resistance *2 a 40 25 10 idcdc1 = 0 ma iregdccd1 consumption current on active *2 a 1 0 ?1 ddvbat1 = 5.5 v dcdc1 = disable vlx1 = 0 v or 5.5 v ilxl1 lx leak current *2 % ? 80 75 ddvbat1 = 3.7 v vdcdc1 = 1.2 v idcdc1 = ? 150 ma effdcdc12 efficiency 2 *2 % ? 90 85 ddvbat1 = 3.4 v vdcdc1 = 2.4 v idcdc1 = ? 150 ma effdcdc11 efficiency 1 dcdc1 (dc-dc step down regulator) *2 a 1.2 1.0 ? from fb1 100% to fb1 70% vb = 3.7 v ilimdcdc1 output over current limit *2 v 1.230 1.200 1.170 idcdc1 = ? 300 ma vout = 1.2 v setting vdcdc1 output voltage reference values typ unit max notes min conditions symbol parameter application information (continued) reference values for design v vbat (ddvbat1 = vb = vin2) = 3.1v to 4.5v, dvdd = 1.85v , dc-dc : co = 4.7 f, lo = 1 h / ldo : co =1.0 f t a = 25 c 2 c unless otherwise noted. notes) *2 :checked by design, not production tested. 10 an30183a ver. aeb *2 s ? ? 1.3 ? t buf bus free time between stop and start condition *2 s ? ? 0.6 ? t su:sto set-up time of stop condition *2 ns 300 ? 20 + 0.1 c b ? t f fall time of both sda and scl signals *2 ns 300 ? 20 + 0.1 c b ? t r rise time of both sda and scl signals *2 ns ? ? 100 ? t su:dat data set-up time *2 s 0.9 ? 0 ? t hd:dat data hold time *2 v ? ? 0.1 v dvdd v io < 2 v, hysteresis 2 of sda, scl vhys2 hysteresis of schmitt trigger input 2 i 2 c bus (bus line specifications) *2 s ? ? 0.6 ? t su:sta set-up time for a repeat start condition *2 s ? ? 0.6 ? t high high period of the scl clock *2 s ? ? 1.3 ? t low low period of the scl clock *2 s ? ? 0.6 the first clock pulse is generated after t hd:sta. t hd:sta hold time (repeated) start condition *2 pf 10 ? ? ? ci capacitance for each i/o pin *2 ns 50 ? 0 ? tsp pulse width of spikes which must be suppressed by the input filter i 2 c bus (internal i/o stage characteristics) *2 ns 250 ? 20 + 0.1 c b bus capacitance : 10 pf to 400 pf i p 6ma (v olmax = 0.6 v) i p : max. sink current tof output fall time from v ihmin to v ilmax *2 v ? ? 0.05 v dvdd v io > 2 v, hysteresis 1 of sda, scl vhys1 hysteresis of schmitt trigger input 1 reference values typ unit max notes min conditions symbol parameter application information (continued) reference values for design v vbat (ddvbat1 = vb = vin2) = 3.1v to 4.5v, dvdd = 1.85v , dc-dc : co = 4.7 f, lo = 1 h / ldo : co =1.0 f t a = 25 c 2 c unless otherwise noted. notes) *2 :checked by design, not production tested. 11 an30183a ver. aeb *2 a 17 8 ? ddvbat1 = vb = vin2 = 3.7 v dcdc1, ldo1 to 4 = off reset= ?h? ibat_4 static consumption current 2 consumption current *2 *3 v ? ? 0.1 v dvdd ? v nl noise margin at the low-level for each connected device i 2 c bus (bus line specifications) (continued) *2 *3 v ? ? 0.2 v dvdd ? v nh noise margin at the high-level for each connected device *2 *3 pf 400 ? ? ? c b capacitive load for each bus line reference values typ unit max notes min conditions symbol parameter notes) *2 :checked by design, not production tested. *3 :the timing of fast-mode devices in i 2 c-bus is specified as the following. all values referred to v ihmin and v ilmax level. s : start condition sr : repeat start condition p : stop condition scl sda t low t f t r t hd;sta t hd;dat t high t su;dat t f t su;sta t hd;sta t sp sr t su;sto t buf ps t r s application information (continued) reference values for design v vbat (ddvbat1 = vb = vin2) = 3.1v to 4.5v, dvdd = 1.85v , dc-dc : co = 4.7 f, lo = 1 h / ldo : co =1.0 f t a = 25 c 2 c unless otherwise noted. notes) *2 :checked by design, not production tested. 12 an30183a ver. aeb dcdc1 input power supply ddvbat1 c5 input for ldo3 and ldo4 power supply vin2 a1 ldo3 output output vldo3 a2 ldo1 on/off control input ldo1on a3 ldo2 output output vldo2 a4 input for ldo1, ldo2 and other vb power supply vb a5 ldo4 output output vldo4 b1 power supply for logic power supply dvdd b2 i 2 c slave address select input asel b3 reference output output vreg b4 ldo1 output output vldo1 b5 reference output output ref c1 control to select power setting input regcnt c2 gnd ground agnd c3 dcdc1 voltage feedback input fb1 c4 reset input for logic input reset d1 i 2 c clock input input scl d2 i 2 c data input/output input/output sda d3 gnd ground ddgnd1 d4 dcdc1 switching output lx1 d5 description type pin name pin no. pin functions pin configuration top view lx1 dd gnd1 dd vbat1 fb1 agnd vldo1 vbat2 sda vreg scl reg cnt ref asel vldo4 reset dvdd vb vldo2 vbon ldo1 on vldo3 vin2 a b c d 54321 notes) concerning detail about pin description, please refer to operation and application information section. vb vldo2 ldo1 on vldo3 vin2 13 an30183a ver. aeb ddgnd1 lx1 ddvbat1 ldo2 dvdd sda asel dcdc1 fb1 1.0 to 3.3 v / 300 ma(min) ldo1 vb scl reset ref ref ldo1on agnd ldo4 1.0 to 3.3 v / 300 ma (min) ldo3 vin2 i 2 c i/f dvdd det tsd vb vb vb dvdd vb dvdd dvdd vb vreg vreg 3m 3m vldo1 vldo4 vldo3 vldo2 1.0 to 3.3 v / 300 ma (min) 1.0 to 3.3 v / 300 ma(min) 0.8 v to 2.4 v / 600 ma(min) regcnt vb dvdd 3m c3 b2 d3 d2 b3 d1 a3 c1 b4 d5 d4 c4 b5 c5 a4 a1 a5 b1 a2 c2 functional block diagram notes) ? this application circuit is an example. the operation of mass production set is not guaranteed. you should perform enough evaluation and verification on the design of mass production set. you are fully responsible for the incorporation of the above application circuit and information in the design of your equipment. ? this block diagram is for explaining functions. part of the block diagram may be omitted, or it may be simplified. 14 an30183a ver. aeb typical characteristics curves (1) output ripple voltage of dc-dc1 v in = 3.7 v, dc-dc1_vout = 1.2 v , l1 = 1 h , cdcdcout1 = 4.7 f dc-dc1 , iout = 0ma vout lx1 dc-dc1 , iout = 100ma dc-dc1 , iout = 600ma vout lx1 vout lx1 15 an30183a ver. aeb typical characteristics curves (continued) (2) load transient of dc-dc1 v in = 3.7 v, dc-dc1_vout = 1.2 v , l1 = 1 h , cdcdcout1 = 4.7 f dc-dc1 , iout = 10 a to 500ma ( t=500ma/usec) vout iout dc-dc1 , iout = 500ma to 10 a ( t=500ma/usec) vout iout 16 an30183a ver. aeb an30183a dc-dc1 efficiency 0 10 20 30 40 50 60 70 80 90 100 1 10 100 1000 load current [ma] efficiency [%] vout=0.8v vout=1.2v vout=1.8v vout=2.4v typical characteristics curves (continued) (3) efficiency of dc-dc1 v in = 3.7 v, dc-dc1_vout = 1.2 v , l1 = 1 h , cdcdcout1 = 4.7 f 17 an30183a ver. aeb typical characteristics curves (continued) (4) load regulation of dc-dc1 v in = 3.7 v, dc-dc1_vout = 1.2 v , l1 = 1 h , cdcdcout1 = 4.7 f load regulation of dc-dc1 1 1.05 1.1 1.15 1.2 1.25 1.3 1.35 1.4 0 100 200 300 400 500 600 load current [ma] vdcdcout1 [v] 18 an30183a ver. aeb line regulation of dc-dc1 1 1.05 1.1 1.15 1.2 1.25 1.3 1.35 1.4 2 2.5 3 3.5 4 4.5 5 5.5 6 vin [v] dcdcout1 [v] typical characteristics curves (continued) (5) line regulation of dc-dc1 iout = 300ma, dc-dc1_vout = 1.2 v, l1 = 1 h , cdcdcout1 = 4.7 f , v in = 2.4v to 5.5v 19 an30183a ver. aeb typical characteristics curves (continued) (6) start up & shut down of dc-dc1 v in = 3.7 v, dc-dc1_vout = 1.2 v, l1 = 1 h , cdcdcout1 = 4.7 f dc-dc1 , rdcdcout1 = no load start up vdcdcout1 i 2 c signal vdcdcout1 i 2 c signal dc-dc1 , rdcdcout1 = no load shut down 20 an30183a ver. aeb typical characteristics curves (continued) (7) start up & shut down of dc-dc1 (continued) v in = 3.7 v, dc-dc1_vout = 1.2 v, l1 = 1 h , cdcdcout1 = 4.7 f dc-dc1 , rdcdcout1 = 4 start up vdcdcout1 i 2 c signal vdcdcout1 i 2 c signal dc-dc1 , rdcdcout1 = 4 shut down 21 an30183a ver. aeb typical characteristics curves (continued) (8) short protection of dc-dc1 v in = 3.7 v, dc-dc1_vout = 1.2 v, l1 = 1 h , cdcdcout1 = 4.7 f iout vout lx 22 an30183a ver. aeb typical characteristics curves (continued) (9) thermal performance of dc-dc1 v in = 3.7 v, dc-dc1_vout = 1.2 v, iload = 600ma , l1 = 1 h , cdcdcout1 = 4.7 f 23 an30183a ver. aeb dc-dc1 , iout = 0ma vout lx1 dc-dc1 , iout = 300ma dc-dc1 , iout = 600ma vout lx1 vout lx1 typical characteristics curves (continued) (10) frequency of dc-dc1 v in = 3.7 v, dc-dc1_vout = 1.2 v, l1 = 1 h , cdcdcout1 = 4.7 f 24 an30183a ver. aeb dc-dc1 , vin = 2.5v vout lx1 dc-dc1 , vin = 3.7v dc-dc1 , vin = 5.5v vout lx1 vout lx1 typical characteristics curves (continued) (11) frequency of dc-dc1 (continued) iout = 300ma, dc-dc1_vout = 1.2 v, l1 = 1 h , cdcdcout1 = 4.7 f 25 an30183a ver. aeb note) the characteristics listed below are reference values derived from the design of the ic and are not guaranteed. operation 1. i 2 c-bus interface a.) basic rules b.) start and stop conditions start condition stop condition sda scl acknowledgement signal from slave acknowledgement signal from receiver start or repeated start condition stop or repeated start condition scl sda msb ack ack 12 789 123 ?89 sr or p sr p s or sr this ic, i2c-bus, is designed to correspond to the standard-mode (100 kbps) and fast-mode(400 kbps) devices in the version 2. 1 of nxp's specification. however, it does not corre spond to the hs-mode (to 3.4 mbps). this ic will operate as a slave device in the i 2 c- bus system. this ic will not operate as a master device. the program operation check of this ic has not been conducted on the multi-master bus system and the mix- speed bus system, yet. the connected confirmation of this ic to the cbus receiver also has not been checked. please confirm with our company if the ic will be used in these mode systems. the i 2 c is the brand of nxp. a high to low transition on the sda line while scl is high is one such unique case. this situation indicates start condition. a low to high transition on the sda line while scl is high defines stop condition. start and stop conditions are always generated by the master. after start condi tion occur, the bus will be busy. the bus is considered to be free again a certain time after the stop condition. every byte put on the sda line must be 8-bits long. the number of bytes that can be transmitted per transfer is unrestricted. each byte has to be followed by an acknowledge bit. data is transferred with the most significant bit (msb) first. d1.) when sub address is not specified d2.) when sub address is specified ex) when writing data into address and reading data from "01 h". sub-address should be assigned first. stop condition ack start condition write mode : 0 data byte sub address slave address a p a a w s stop condition ack start condition read mode : 1 data byte slave address p a a r s data byte sub address 01h slave address ap a a 0 s ap data byte slave address a 1 s write read stop condition acknowledge bit start condition write mode : 0 repeated start condition read mode : 1 ack ack data byte slave address sub address slave address s ap a a 1 a 0 s d.) data format 1 1 a6 6fh x 1 1 0 0 1 1 high 6eh hex 1 a5 x r/w 1 a1 0 a3 0 0 1 low a0 a2 a4 pin asel slave address write mode read mode when data is read without assi gning sub-address, it is possible to read the value of sub-address specified in write mode immediately before. 26 an30183a ver. aeb gpen ? ? ? gpld2 gpld3 ldo1en sel ? ? ld1ps ld2ps ld3ps dd1on ? ld1on ? ld4ps gpdd vl3[3:0] vl1[3:0] vdc1[3:0] ld2on ? ld3on ? ? ? name pscnt r/w 05h 0 0 0 0 0 0 ? ? default ? ? ? ? name ensel r/w 06h 1 ? ? ? ? ? ? ? default vl4[3:0] name dac3 r/w 03h 0 1 0 1 0 0 1 1 default gpld4 name group r/w 04h 0 0 0 1 1 1 1 1 default ? name dac1 r/w 01h 0 0 0 1 0 1 1 1 default vl2[3:0] name dac2 r/w 02h 1 0 0 1 0 0 0 0 default default name bit 0 0 0 0 0 0 0 0 ld4on ? ? cnt r/w 00h r/w register name sub address d5 d6 d7 data d0 d1 d2 d3 d4 dcdc1 ? ldo1 ldo2 ldo3 1.2v ? 1.85v 1.0v 2.6v 2.8v ? ? ldo4 ? ? default voltage note) the characteristics listed below are reference values derived from the design of the ic and are not guaranteed. operation ( continued ) 2. register map 27 an30183a ver. aeb dd1on ? ld1on ld2on ld3on default name bit 0 0 0 0 0 0 0 0 ld4on ? ? cnt r/w 00h r/w register name sub address d5 d6 d7 data d0 d1 d2 d3 d4 d5 : ldo4 on/off select register [0] : off (default) [1] : on d4 : ldo3 on/off select register [0] : off (default) [1] : on d3 : ldo2 on/off select register [0] : off (default) [1] : on d2 : ldo1 on/off select register [0] : off (default) [1] : on d0 : dcdc1 on/off select register [0] : off (default) [1] : on note) the characteristics listed below are reference values derived from the design of the ic and are not guaranteed. operation ( continued ) 3. register map details 28 an30183a ver. aeb 0 0 0 vdc1[3:0] ? name dac1 r/w 01h 1 0 1 1 1 default bit r/w register name sub address d5 d6 d7 data d0 d1 d2 d3 d4 d3-0 : dcdc1 register for output voltage setup 2.40 1.85 1.80 1.65 1.50 1.40 1.30 1.20 (default) 1.15 1.10 1.05 1.00 0.95 0.90 0.85 0.80 output voltage [v] 0 0 1 1 1 0 1 1 vdc1[3:0] 0 0 0 0 1 0 0 0 0 1 0 0 1 1 0 0 0 0 1 0 1 0 1 0 0 1 1 0 1 1 1 0 0 0 0 1 1 0 0 1 0 1 0 1 1 1 0 1 0 1 1 1 1 1 1 1 d4 d5 d6 d7 note) the characteristics listed below are reference values derived from the design of the ic and are not guaranteed. operation ( continued ) 3. register map details 29 an30183a ver. aeb 1 0 0 vl1[3:0] vl2[3:0] name dac2 r/w 02h 1 0 0 0 0 default bit r/w register name sub address d5 d6 d7 data d0 d1 d2 d3 d4 3.30 3.00 2.85 2.80 2.70 2.60 1.85 1.80 1.70 1.60 1.50 1.40 1.30 1.20 1.10 1.00 (default) output voltage [v] 0 0 1 1 1 0 1 1 vl2[3:0] 0 0 0 0 1 0 0 0 0 1 0 0 1 1 0 0 0 0 1 0 1 0 1 0 0 1 1 0 1 1 1 0 0 0 0 1 1 0 0 1 0 1 0 1 1 1 0 1 0 1 1 1 1 1 1 1 d4 d5 d6 d7 3.30 3.00 2.85 2.80 2.70 1.90 1.85 (default) 1.80 1.70 1.60 1.50 1.40 1.30 1.20 1.10 1.00 output voltage [v] 0 0 1 1 1 0 1 1 vl1[3:0] 0 0 0 0 1 0 0 0 0 1 0 0 1 1 0 0 0 0 1 0 1 0 1 0 0 1 1 0 1 1 1 0 0 0 0 1 1 0 0 1 0 1 0 1 1 1 0 1 0 1 1 1 1 1 1 1 d0 d1 d2 d3 d7-4 : ldo2 register for output voltage setup d 3-0 : ldo1 register for output voltage setup note) the characteristics listed below are reference values derived from the design of the ic and are not guaranteed. operation ( continued ) 3. register map details 30 an30183a ver. aeb 0 1 0 vl3[3:0] vl4[3:0] name dac3 r/w 03h 1 0 0 1 1 default bit r/w register name sub address d5 d6 d7 data d0 d1 d2 d3 d4 3.30 3.00 2.85 2.80 (default) 2.70 2.60 1.85 1.80 1.70 1.60 1.50 1.40 1.30 1.20 1.10 1.00 output voltage [v] 0 0 1 1 1 0 1 1 vl4[3:0] 0 0 0 0 1 0 0 0 0 1 0 0 1 1 0 0 0 0 1 0 1 0 1 0 0 1 1 0 1 1 1 0 0 0 0 1 1 0 0 1 0 1 0 1 1 1 0 1 0 1 1 1 1 1 1 1 d4 d5 d6 d7 3.30 3.00 2.85 2.80 2.70 2.60 (default) 1.85 1.80 1.70 1.60 1.50 1.40 1.30 1.20 1.10 1.00 output voltage [v] 0 0 1 1 1 0 1 1 vl3[3:0] 0 0 0 0 1 0 0 0 0 1 0 0 1 1 0 0 0 0 1 0 1 0 1 0 0 1 1 0 1 1 1 0 0 0 0 1 1 0 0 1 0 1 0 1 1 1 0 1 0 1 1 1 1 1 1 1 d0 d1 d2 d3 d7-4 : ldo4 register for output voltage setup d 3-0 : ldo3 register for output voltage setup note) the characteristics listed below are reference values derived from the design of the ic and are not guaranteed. operation ( continued ) 3. register map details 31 an30183a ver. aeb gpen ? ? gpdd ? default name bit 0 0 0 1 1 1 1 1 gpld2 gpld3 gpld4 group r/w 04h r/w register name sub address d5 d6 d7 data d0 d1 d2 d3 d4 d7 : external pin on/off cont rol for ldo4 select register [0] : i2c control [1] : external pin control (default) d6 : external pin on/off cont rol for ldo3 select register [0] : i2c control [1] : external pin control (default) d5 : external pin on/off cont rol for ldo2 select register [0] : i2c control [1] : external pin control (default) d3 : external pin on/off cont rol for dcdc1 select register [0] : i2c control [1] : external pin control (default) d0 : external pin control permit register [0] : external pin control valid (default) [1] : external pin control invalid note) the characteristics listed below are reference values derived from the design of the ic and are not guaranteed. operation ( continued ) * please set it to normal mode when ldo starts. 3. register map details 32 an30183a ver. aeb 33 an30183a ver. aeb ld1ps ld2ps ld3ps ld4ps ? default name bit 0 0 0 0 0 0 ? ? ? ? ? pscnt r/w 05h r/w register name sub address d5 d6 d7 data d0 d1 d2 d3 d4 d3 : ldo4 power save mode select register [0] : normal mode (default) [1] : power save mode d2 : ldo3 power save mode select register [0] : normal mode (default) [1] : power save mode d1 : ldo2 power save mode select register [0] : normal mode (default) [1] : power save mode d0 : ldo1 power save mode select register [0] : normal mode (default) [1] : power save mode *please set it to normal mode when ldo starts. note) the characteristics listed below are reference values derived from the design of the ic and are not guaranteed. operation ( continued ) 3. register map details 34 an30183a ver. aeb ldo1en sel ? ? ? ? default name bit 1 ? ? ? ? ? ? ? ? ? ? ensel r/w 06h r/w register name sub address d5 d6 d7 data d0 d1 d2 d3 d4 d0 : ldo1ensel [0] : ldo1on control invalid [1] : ldo1on control valid (default) note) the characteristics listed below are reference values derived from the design of the ic and are not guaranteed. operation ( continued ) 3. register map details 35 an30183a ver. aeb 2.4 v 1.24 v 2.2 v 2.1 v 1.5 v 1.4 v nm ps nm nm ps nm @ 150 s nm ps nm vbat (external input signal) ref (ic output signal) vreg (ic output signal) regw (ic inner signal) dvdd det (ic inner signal) reset (external input signal) ldo1on (external input signal) vldo1 (ic output signal) vldo 2/3/4 (ic output signal) dcdc1 (ic output signal) osc (ic inner signal) dvdd (external input signal) i2c input ps ? nm ps ? nm all registers are initialized (ldo and dcdc are turned off) ldo* stop is possible even in ps mode ldo1 starts in nm mode i2c acceptance starts i2c acceptance stops dvdd_det:high and reset:high = i2c acceptance on dvdd_det:low and reset:low = i2c acceptance off at dcdc-start at ldo-start i2c input i2c stops pin ldo1 stops pin ldo1 starts i2c starts i2c stops i2c starts i2c stops i2c starts note) the characteristics listed below are reference values derived from the design of the ic and are not guaranteed. operation ( continued ) 4. timing chart (sequence ? 1 (dvdd input externally)) 36 an30183a ver. aeb 2.4 v 1.24 v 2.2 v 2.1 v 1.5 v 1.4 v nm nm nm 1.2 v 0.45 v @ 150 s 1.2 v 0.45 v vbat (external input signal) ref (ic output signal) vreg (ic output signal) regw (ic inner signal) dvdd det (ic inner signal) reset (external input signal) ldo1on (external input signal) vldo1 (ic output signal) vldo 2/3/4 (ic output signal) dcdc1 (ic output signal) osc (ic inner signal) dvdd (external input signal) i2c acceptance starts i2c acceptance stops dvdd_det:high and reset:high = i2c acceptance on at dcdc-start at ldo-start i2c stops i2c starts i2c starts i2c stops i2c stops i2c starts ldo1 starts in nm mode pin ldo1 starts pin ldo1 stops note) the characteristics listed below are reference values derived from the design of the ic and are not guaranteed. 4. timing chart (sequence ? 2 (ldo1on = fixed vbat)) operation ( continued ) 37 an30183a ver. aeb 1.24 v 1.5 v 1.4 v 2.4 v 2.2 v 2.1 v @ 150 s 1.5 v 1.4 v vbat (external input signal) ref (ic output signal) vreg (ic output signal) regw (ic inner signal) dvdd det (ic inner signal) reset (external input signal) ldo1on (external input signal) vldo1 (ic output signal) vldo 2/3/4 (ic output signal) dcdc1 (ic output signal) osc (ic inner signal) dvdd:vldo1 (external input signal) vldo1 is connected directly with dvdd i2c acceptance starts i2c acceptance stops dvdd_det:high and reset:high = i2c acceptance on dvdd_det:low and reset:low = i2c acceptance off at dcdc-start at ldo-start pin ldo1 stops pin ldo1 starts i2c starts i2c stops i2c starts i2c stops note) the characteristics listed below are reference values derived from the design of the ic and are not guaranteed. operation ( continued ) 4. timing chart (sequence ? 3 (vldo1 = connected dvdd)) 38 an30183a ver. aeb 2.4v 2.2v 2.1v nm ps nm nm ps nm address:04h data:61h 00h 18h nm 05h 02h 05h 00h 00h 10h 05h 01h 05h 00h nm ps nm 00h 19h 00h 3dh 05h 09h 05h 00h 00h 18h nm ps nm nm nm ps nm 05h 04h 00h 00h 01h xxh 02h xxh 03h xxh initial setting control resistor @ 150 s regcnt (external input signal) vbat reset dvdd (external input signal) vreg (ic output signal) regw (ic inner signal) i 2 c (external input signal) vldo3 (ic output signal) pin ldo1 starts pin ldo1 stops dcdc1 (ic output signal) all ldos can also be stopped in ps mode vldo4 (ic output signal) i2c starts i2c stops vldo2 (ic output signal) pin regcnt starts i2c starts i2c stops pin regcnt stops ldo1on (external input signal) vldo1 (ic output signal) pin regcnt stops i2c starts i2c stops pin regcnt starts i2c starts i2c stops i2c stops i2c starts note) the characteristics listed below are reference values derived from the design of the ic and are not guaranteed. operation ( continued ) 4. timing chart (sequence ? 4 (ldo2/3 are controlled by regcnt)) 39 an30183a ver. aeb address:04h data:61h 00h 18h 05h 02h 05h 00h 00h 10h 05h 01h 05h 00h 00h 19h 00h 3dh 05h 09h 05h 00h 00h 18h 05h 04h 00h 00h 01h xxh 02h xxh 03h xxh nm nm nm nm i 2 c (external input signal) vldo3 (ic output signal) regcnt (external input signal) vldo2 (ic output signal) pin regcnt stops ldo2/3 are controlled by regcnt only ldo2 is controlled by regcnt no regcnt control i2c starts i2c stops i2c stops pin regcnt starts pin regcnt starts pin regcnt starts i2c stops note) the characteristics listed below are reference values derived from the design of the ic and are not guaranteed. 4. timing chart (sequence ? 4 (ldo2/3 are controlled by regcnt)) (continued) operation ( continued ) 40 an30183a ver. aeb < operation explanation > (1) the overcurrent protection operates at about 1 a (typ). (2) the ground protection sequence is implemented when the output voltag e decreases to about 70% of the set voltage. (3) the ground short protection operates intermittently. (2 ms : on, 16 ms : off) output current [a] pendency characteristic ground short protection about 70% of vout intermittent operation area overcurrent protection (about 1 a) ground short protection hysteresis output voltage [v] about 150 ma operation explanation chart 6. dac voltage accuracy 2.40 1.85 1.80 1.65 1.50 1.40 1.30 1.20 (default) 1.15 1.10 1.05 1.00 0.95 0.90 0.85 0.80 output voltage [v] 3.0 3.0 4.0 3.0 3.0 4.0 3.0 2.5 3.5 4.0 5.0 6.0 6.0 6.5 6.5 8.5 accuracy [%] 0 0 1 1 1 0 1 1 vdc1[3:0] 0 0 0 0 1 0 0 0 0 1 0 0 1 1 0 0 0 0 1 0 1 0 1 0 0 1 1 0 1 1 1 0 0 0 0 1 1 0 0 1 0 1 0 1 1 1 0 1 0 1 1 1 1 1 1 1 d0 d1 d2 d3 dcdc1 (vbat = 3.7 v , iout = ?300 ma) note) the characteristics listed below are reference values derived from the design of the ic and are not guaranteed. operation ( continued ) 5. dc-dc protection operation 41 an30183a ver. aeb ldo vbat = 3.7 v (normal-mode : iout = ? 150 ma, ps-mode : iout = ? 5 ma) ldo2 to 4 ldo1 ldo2 to 4 ldo1 ps-mode normal-mode 3.0 3.0 3.0 3.0 3.0 ? 2.5 2.5 3.0 3.0 3.0 3.0 3.0 4.0 4.0 4.5 5.0 accuracy [%] 3.0 3.0 3.0 3.0 3.0 3.0 ? 2.5 3.0 3.0 3.0 3.0 3.0 4.0 4.0 4.5 5.0 3.0 3.0 3.0 3.0 3.0 ? 2.5 2.5 3.0 3.0 3.0 3.0 3.0 4.0 4.0 4.5 5.0 3.0 3.0 3.0 3.0 3.0 3.0 ? 2.5 3.0 3.0 3.0 3.0 3.0 4.0 4.0 4.5 5.0 1.90 0 1 0 1 3.30 3.00 2.85 2.80 2.70 2.60 1.85 1.80 1.70 1.60 1.50 1.40 1.30 1.20 1.10 1.00 output voltage [v] 0 0 1 1 1 0 1 1 vl1[3:0] 0 0 0 0 1 0 0 0 0 1 0 0 1 1 0 0 0 0 1 0 1 0 1 0 0 1 1 0 1 1 1 0 0 0 0 1 1 0 0 1 1 1 0 1 0 1 1 1 1 1 1 1 d0 d1 d2 d3 note) the characteristics listed below are reference values derived from the design of the ic and are not guaranteed. operation ( continued ) 6. dac voltage accuracy (continued) 42 an30183a ver. aeb (1) start up ldo1 (2) start up ldo2/3/4 and dcdc1 ldo1 ldo1on vldo*0.9 <100 s ldo2/3/4 regcnt vldo*0.9 <100 s dcdc1 regcnt vout*0.9 <500 s ldo1 sda vldo*0.9 <60 s ldo2/3/4 sda . vldo*0.9 <60 s dcdc1 sda vout*0.9 <500 s start up by ldo1on start up by i2c start up by regcnt start up by i2c start up by regcnt start up by i2c note) the characteristics listed below are reference values derived from the design of the ic and are not guaranteed. operation ( continued ) 7. start up timing from ldo1on , regcnt and i 2 c 43 an30183a ver. aeb application information 1.application circuit and evaluation board note) the characteristics listed below are reference values derived from the design of the ic and are not guaranteed. figure : top layer with silk screen ( top view ) with evaluation board figure : bottom layer with silk screen ( bottom view ) with evaluation board figure : application circuit notes) this application circuit and layout is an example. the ope ration of mass production set is not guaranteed. you should perfor m enough evaluation and verification on the design of mass production set. you are fully responsible for the incorporation of the above application circuit and information in the design of your equipment. dcdcout1 vin2 vb an30183a agnd vreg ldo4 ldo3 ldo2 ldo1 ref lx1 fb1 ddgnd1 reset ldo1on sda scl asel cout3 cout4 cvreg cref cout2 cout1 l1 cdcdcout1 cv1 cv2 regcnt ddvbat1 c1 dvdd cd1 44 an30183a ver. aeb application information (continued) 2.recommended component note) the characteristics listed below are reference values derived from the design of the ic and are not guaranteed. grm185b31a105ke35 murata 1.0f 1 cref 1.0f 1.0f 1.0f 1.0f 1.0f 4.7f 1.0 h 0.1f 4.7f 4.7f 4.7f value 1 1 1 1 1 1 1 1 1 1 1 qty grm185b31a105ke35 murata cout2 grm185b31a105ke35 murata cout3 grm185b31a105ke35 murata cout4 grm185b31a105ke35 murata cout1 grm21bb31a475ka74 murata cdcdcout1 GRM188B11C104KA01 murata cd1 mipsz2012d1r0 fdk l1 grm21bb31c475ka87 murata vc2 grm21bb31c475ka87 murata cv1 grm21bb31c475ka87 murata c1 grm185b31a105ke35 murata cvreg part number manufacturer reference designator figure : recommended component 45 an30183a ver. aeb package information ( reference data ) unit:mm bump : snagcu reroute material : cu body materia l : br/sb free epoxy resin outline drawing package code : xbga020-w-1621ael 46 an30183a ver. aeb important notice 1.the products and product specificat ions described in this book are subject to change without notice for modification and/or improvement. at the final stage of your design, purchasing, or use of the products, therefore, ask for the most up-to-date product standards in advance to ma ke sure that the latest specifications satisfy your requirements. 2.when using the lsi for new models, verify the safe ty including the long-term reliability for each product. 3.when the application system is designed by using this lsi, be sure to confirm notes in this book. be sure to read the notes to descr iptions and the usage notes in the book. 4.the technical information described in this book is inten ded only to show the main characteristics and application circuit examples of the products. no license is granted in and to any intellectual property right or other right owned by panasonic corporation or any other company. therefore, no responsibility is assumed by our company as to the infringement upon any such right owned by any other company which may arise as a result of the use of technical information de-scribed in this book. 5.this book may be not reprinted or r eproduced whether wholly or partially, without the prior written permission of our company. 6.this lsi is intended to be used for general electronic equipment. consult our sales staff in advance for information on the following applications: special applications in which exceptional quality and reliability are required, or if the failu re or malfunction of this lsi may directly jeopardize life or harm the human body. any applications other than t he standard applications intended. (1) space appliance (such as artificial satellite, and rocket) (2) traffic control equipment (such as fo r automobile, airplane, train, and ship) (3) medical equipment for life support (4) submarine transponder (5) control equipment for power plant (6) disaster prevention and security device (7) weapon (8) others : applications of which reliabili ty equivalent to (1) to (7) is required it is to be understood that our company sh all not be held responsible for any damage incurred as a result of or in connection with your using the lsi described in this book for any special application, unless our company agrees to your using the lsi in this book for any special application. 7.this lsi is neither designed nor intended for use in aut omotive applications or envir onments unless the specific product is designated by our company as comp liant with the iso/ts 16949 requirements. our company shall not be held responsible for any damage incurred by you or any third party as a result of or in connection with your using the lsi in aut omotive application, unless our compan y agrees to your using the lsi in this book for such application. 8.if any of the products or technical in formation described in this book is to be exported or provided to non-residents, the laws and regulations of the exporting country, especially , those with regard to security export control, must be observed. 9. please use this product in compliance with all applicable la ws and regulations that regula te the inclusion or use of controlled substances, including withou t limitation, the eu rohs directive. our company shall not be held responsible for any dama ge incurred as a result of your using the lsi not complying with the applicable laws and regulations. 47 an30183a ver. aeb usage notes 1. when designing your equipment, comply with the range of absolute maximum rating and the guaranteed operating conditions (operating power supply voltage and operating environment etc. ). especially, please be careful not to exceed the range of absolute maximum rati ng on the transient state, such as power-on, power-off and mode-switching. otherwise, we will not be liable for any defect which may arise later in your equipment. even when the products are used within the guaranteed val ues, take into the consideration of incidence of break down and failure mode, possible to occur to semi conductor products. measures on the systems such as redundant design, arresting the spread of fire or preventing glitch are reco mmended in order to prevent physical injury, fire, social damages, for example, by using the products. 2. comply with the instructions for use in order to pr event breakdown and characteristics change due to external factors (esd, eos, thermal stress and mechanical stress) at the time of handling, mo unting or at customer's process. when using products for which damp-proof packing is required, satisfy the conditions, such as shelf life and the elapsed time since first opening the packages. 3. pay attention to the direction of lsi. when mounting it in the wrong directi on onto the pcb (printed-circuit-board), it might smoke or ignite. 4. pay attention in the pcb (printed-circuit-board) pattern layout in order to prevent damage due to short circuit between pins. in addition, refer to the pin description for the pin configuration. 5. perform a visual inspection on the pcb before applying power, otherwise damage might happen due to problems such as a solder-bridge between the pins of t he semiconductor device. also, perform a full technical verification on the assembly quality, because the same damage possibly can happen due to conductive substances, such as solder ball, that adhere to the lsi during transportation. 6. take notice in the use of this pr oduct that it might break or occasionally smoke when an abnormal state occurs such as output pin-vcc short (power supply fault), out put pin-gnd short (ground faul t), or output-to-output-pin short (load short) . and, safety measures such as an installation of fuses are recommended becaus e the extent of the above- mentioned damage and smoke emission will depend on the current capability of the power supply. 7. the protection circuit is for maintaining safety agai nst abnormal operation. theref ore, the protection circuit should not work during normal operation. especially for the thermal protection ci rcuit, if the area of safe operation or the absolute maximum rating is momentarily exceeded due to output pin to vcc short (pow er supply fault), or output pin to gnd short (ground fault), the lsi might be damaged before t he thermal protection circuit could operate. 8. unless specified in the product specifications, make sure that negative voltage or excessive voltage are not applied to the pins because the device might be damage d, which could happen due to negative voltage or excessive voltage generated during the on and off timing when the inductive load of a motor coil or actuator coils of optical pick-up is being driven. 9. the product which has spec ified aso (area of safe oper ation) should be operated in aso 10. verify the risks which might be caused by the malfunctions of external components. 11. connect the metallic plates on the back side of the lsi with their respecti ve potentials (agnd, pvin, lx). the thermal resistance and the electrical characteristics ar e guaranteed only when the meta llic plates are connected with their respective potentials. request for your special attention and precautions in using the technical information and semiconductors described in this book (1) if any of the products or technical information described in this book is to be exported or provided to non-residents, the laws and regulations of the exporting country, especially, those with regard to security export control, must be observed. (2) the technical information described in this book is intended only to show the main characteristics and application circuit examples of the products. no license is granted in and to any intellectual property right or other right owned by panasonic corporation or any other company. therefore, no responsibility is assumed by our company as to the infringement upon any such right owned by any other company which may arise as a result of the use of technical information described in this book. (3) the products described in this book are intended to be used for general applications (such as office equipment, communications equipment, measuring instruments and household appliances), or for specific applications as expressly stated in this book. consult our sales staff in advance for information on the following applications: ? special applications (such as for airplanes, aerospace, automotive equipment, traffic signaling equipment, combustion equipment, life support systems and safety devices) in which exceptional quality and reliability are required, or if the failure or malfunction of the products may directly jeopardize life or harm the human body. it is to be understood that our company shall not be held responsible for any damage incurred as a result of or in connection with your using the products described in this book for any special application, unless our company agrees to your using the products in this book for any special application. (4) the products and product specifications described in this book are subject to change without notice for modification and/or im- provement. at the final stage of your design, purchasing, or use of the products, therefore, ask for the most up-to-date product standards in advance to make sure that the latest specifications satisfy your requirements. (5) when designing your equipment, comply with the range of absolute maximum rating and the guaranteed operating conditions (operating power supply voltage and operating environment etc.). especially, please be careful not to exceed the range of absolute maximum rating on the transient state, such as power-on, power-off and mode-switching. otherwise, we will not be liable for any defect which may arise later in your equipment. even when the products are used within the guaranteed values, take into the consideration of incidence of break down and failure mode, possible to occur to semiconductor products. measures on the systems such as redundant design, arresting the spread of fire or preventing glitch are recommended in order to prevent physical injury, fire, social damages, for example, by using the products. (6) comply with the instructions for use in order to prevent breakdown and characteristics change due to external factors (esd, eos, thermal stress and mechanical stress) at the time of handling, mounting or at customer's process. when using products for which damp-proof packing is required, satisfy the conditions, such as shelf life and the elapsed time since first opening the packages. (7) this book may be not reprinted or reproduced whether wholly or partially, without the prior written permission of our company. 20100202 |
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